Design For Cost

In 1789, Benjamin Franklin, who achieved the fame and stature of President of the United States without ever having to actually serve in that capacity, famously observed, "In this world nothing can be said to be certain, except death and taxes." Today, more than 200 years later, it appears that one more item can be appended to Franklin's list of certainties: Cost, always a key consideration in IC design, has become increasingly important, increasingly earlier in the IC design flow.

While this statement might seem like a prima facie observation to many industry insiders, careful analysis demonstrates that the most stunning aspect of cost in the design flow is how long cost has remained a simple business/marketing problem. On some nebulous date after the turn of this century, cost crossed over into the realm of engineering problems, where it will certainly remain and where it certainly belongs.

In the early 2000s, a number of seemingly unrelated events converged with a series of subtle trends, forcing cost to cross an imaginary line. This line separated the business side, where cost had resided for decades as an inevitable, yet largely unpredictable byproduct, or output of the design flow, from the engineering side where cost can now exist quite comfortably as a front-loaded and accurately predictable input.

The confluence of events and attitudes at the dawn of the 21st century caused the tech bubble - representing a high watermark for the IC design industry - to burst, rather unceremoniously. The resulting slump in the American economy forced corporations to explore other global markets. Technology companies previously engaged in marketing their performance and feature-driven consumer electronics goods (i.e., cellular phones, laptops, PDAs) to North America and Europe, found themselves scrambling to reengineer these products to meet the lower price points dictated by rapidly expanding, high-growth markets, such as China and India.

Business leaders found it relatively easy to identify continuously mounting price pressures as largely responsible for the emergence of cost as the key differentiator between their competing brands. When mass-market products, such as cell phones, became available with every imaginable option and features and performance came to be viewed as essentially interchangeable between brands, cost filled the vacuum as the key differentiator that could fuel a brand's success.

Thus, as price pressures mounted on final products, sensitivity to cost trickled back down the design flow to the desk of the design manager. Having arrived at this problem solver's desk, cost gradually assumed a place near the top of the list of chip designers' concerns and commitments, which has always and still includes such items as features, performance and time-to-market. And, similar to these more traditional engineering-centric concerns, cost can be managed most effectively through scientific methodology. When engineering decisions, large and small, can be analyzed with respect to their financial implications, then and only then will the dark mysteries surrounding the means of calculating an accurate estimation of final packaged chip cost be exposed - illuminated, as it were, by the bright light of quantification. Such analysis is not as difficult as it might seem at first blush, given the application of the proper tools at the earliest possible stage in the design flow.

As one example, an IC design team with the capability to conduct a computer-aided exploration of a potential chip design across varying process nodes, intellectual property (IP) libraries and chip architectures could ultimately achieve its stated feature and performance goals, while also reducing the cost of the final chip. In essence, they can effectively determine a product's technical and economic viability.

However, in an effort to mitigate risk, IC design teams tend to gravitate towards technologies and IP options with which they are already familiar. This mindset obviously discourages exploration across alternative implementation options.

Further, some designers may be laboring under the false assumption that making refinements to these parameters results in only minor variations to their final product. In fact, selecting a different process variant or IP library may affect a parameter, such as leakage, up to an order of magnitude, which naturally carries profound technical and economic ramifications for the final chip.

Design teams should spend time, early in the design stage, exploring their design in the context of multiple implementation options to understand which set of parameters will let them reach performance and functional goals, while still maintaining control over the economic implications of their decisions. This concept comprises the core of what is known as the design for cost paradigm.

Think Outside the Die

Several years ago, Taco Bell, keen on encouraging fast-food franchise patrons to break the hamburger habit, introduced one of the industry's most clever advertising taglines, "Think outside the bun." If proponents of the emergent philosophy of design for cost were seeking a means to "sell'' these ideas to members of the IC design community, they could scarcely wish for a better tagline than "think outside the die."

The electronic design automation (EDA) industry's response to the increasingly urgent cost pressures being visited upon its customers was to produce, under the aegis of design for manufacturing (DFM), a series of tools aimed primarily at optimizing yield during and after implementation. DFM tools have proven effective at increasing the number of good chips per die, thus saving pennies or nickels per chip.

Many, if not most, of the EDA tools developed expressly to accommodate the DFM mindset, essentially place a figurative bandaid over an open wound yield that historically hemorrhaged money. It is debatable whether the advent of DFM solved the EDA industry's problem (i.e., give our customers an answer quickly); what is absolutely certain is that it has not solved the semiconductor industry's problem.

To solve that problem on a long-term basis, design teams and their EDA tools will need to "think outside the die" - that is, far beyond its size, shape and cost. From an engineering standpoint, improving die yield was a relatively easy fix; in terms of cost savings, it is analogous to using the fine-tuning knob on an old radio to make minor adjustments on the back-end after the key components of that particular signal or chip have been identified.

What is sorely needed, however, is a tool that can