Integrated Ccuit Design

Integrated Circuit Design

Full Adder Project

Design and test of a three-bit dynamic latch

To start I need to build a single bit dynamic latch (schematic and circuit shown below). The latch works using two clock pulses, when the first clock is high the input will be stored so that when the second clock is high the output will be set to the stored input and remain to that value until the next clock. A three-bit dynamic latch contains 3 non-inverting dynamic latch cells made by using the ECIF buildings block at mask level within Chipwise. So I will start by building the one-bit latch…

One-Bit Latch

The output graph should look a little like this…

So If I recreate this circuit as a STX diagram in Chipwise I get the following…

So I check for errors and if all clear I can proceed to generate my ECIF diagram…

With the ECIF diagram generated I need to extract and run DRC to test for any errors.

To simulate I need to create an input pulse along with four clock pulses (two clocks and then the NOT clock of each). I will also need to set the vdd to 5V and initialize the output to 0V.

You can see that this simulation has probes on the input output clock 1 and clock 2. The simulation has a run time of 400ns sampling every 2ns. Below shows the result from simulating…

You can see that the outputs are correct and look almost identical to my predicted graph. So no I have a fully working latch I can now build the three-bit latch.

Three-bit Latch

The three-bit latch can be used to align three pulse so that the switch at the same time which gives it a multitude of uses. To make the three-bit latch I am going to place three one-bit latches side by side so that the vdd, clk1, clk2, clk1/, clk2/ and gnd line up.

I also need to rename the inputs and outputs so that they have individual names. When building with blocks you start with an empty ECIF diagram. Below shows the three-bit latch ECIF diagram...

To simulate this I need to make an extra two input pulses and observe the extra corresponding outputs. Keeping similar settings to the one-bit version. This is the final simulation settings window. The input pulse has been made to have different starting intervals to view latching effect more clearly.

Here is the output from the simulation…

So now you can now see that the output have been aligned to start and finish at the same time. But the input signal width is larger than the output width due to the distance between pulses of clock 2.

Design and test of a Full Adder

To build a full adder I am going to combine two half adders. The following circuit shows a sum circuit which is equivalent to a half adder without the carry. The logic of the circuit consists of a NAND gate and a NOR gate and so has the following logic function…

The truth table of this function will be as flows…

Input Output

A B F

0 0 0

0 1 1

1 0 1

1 1 0

Here is the circuit of the function…

So building this circuit produced the following STX diagram. Then generating this to produce the ECIF diagram for simulation…

To simulate this circuit I only need to change inputs "a" and "b" so that all the combinations of the truth table are produced. To do this I just need to make identical pulses but make them overlap.

So this simulation is going to run for 100ns and sample every 2ns. With probes of "a", "b", "f" and "y".

By comparing this result to the truth table you can see it is giving the correct results.

Full Adder

The full adder is made from two half adders and has the following truth table and logic function…

Input Output

A B C S

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Now I need to connect the two half adders to make my full adder. To connect them I place them next to one another and connect the f output of the first adder to one of the inputs of the second adder. In my circuit I have connect input "a" of the second adder to the first f. with this all connected I need to make new individual labels.

To simulate this I need to create three pulses that will recreate every combination of the truth table, hence the pulse frequencies being, a = 2b = 4c. Below shows the settings